1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a pad structure for relieving a stress applied to a barrier insulation film of a semiconductor device.
2. Discussion of Related Art
In general, all semiconductor memory devices manufactured by using silicon wafers have a pad structure. The pad structure opens a part of a passivation layer on an upper metal layer such as a second metal layer, thereby exposing the upper metal layer. The pad structure is operated as a connection means installed between the inside and outside of the semiconductor device, for supplying a voltage to the semiconductor device and inputting or outputting a data to/from the semiconductor device according to a wire bonding process. The pad structure is one of the major factors that must be considered in manufacturing of the semiconductor device. In the case that the pad structure of the semiconductor device is not reliable, the semiconductor device is not usable.
The pad structure must satisfy the following conditions. First, the pad structure must be formed to minimize a pad stress. The pad stress seriously reduces the adhesive strength of the wire bonding and causes pad lifting. Second, the pad structure must be foamed to maximize a wire bonding strength. Third, the pad structure must be formed to minimize a pad capacitance. If the pad capacitance exists, the semiconductor device may be deteriorated due to the data inputted/outputted through the pad at a speed of a few ns (nano second), and the wire bonding may be separated. The disadvantages of the conventional pad structure will now be explained in detail with reference to FIG. 1.
FIG. 1 is a cross-sectional diagram illustrating a pad structure of a conventional semiconductor device in a back-end process of a NAND flash memory device. FIG. 2 is a partial layout diagram illustrating the conventional semiconductor device having the pad structure of FIG. 1. FIG. 3 is a state diagram illustrating state variations of a silicon nitride film by influences of a thermal stress in the pad structure of the conventional semiconductor device.
Referring to FIG. 1, the pad structure in the back-end process of the NAND flash memory device has a sequentially-stacked structure of a semiconductor substrate 102, a field oxide film 104, a silicon nitride film 106 for a self aligned contact, a first interlayer insulation film 108, a first metal layer 110, a trench stop silicon nitride film 112, an insulation film 114 for a trench, a second metal contact stop silicon nitride film 116, a second interlayer insulation film 118 and a second metal layer 120. Three layers, namely, the silicon nitride film 106 for the self aligned contact, the trench stop silicon nitride film 112 and the second metal contact stop silicon nitride film 116 are silicon nitride films. The silicon nitride films 106, 112 and 116 are used as barrier layers in an etching process by using a select ratio of an oxide to a nitride. As shown in FIG. 2, in the pad structure, the silicon nitride films 106, 112 and 116 are coupled over the outside of a pad region PR formed by partially exposing the second metal layer 120 as well as the inside of the pad region PR, to cover the whole chip.
On the other hand, the silicon nitride film has different thermal properties from those of the upper and lower layers. That is, as compared with a layer including an oxide or polysilicon oxide, the silicon nitride film shows a very high thermal stress. For example, a thermal stress constant of the oxide film SiO2 is 2˜4×109 dyne/cm2, and a thermal stress constant of the silicon nitride film Si3N4 is 9˜10×109 dyne/cm2. Therefore, the thermal stress constant of Si3N4 is larger than that of SiO2 by about 2.5 to 4.5 times.
As depicted in FIG. 3, such thermal stress differences cause lifting between the lower layers 104, 108 and 114 including oxides and the upper layers 106, 112 and 116 including nitrides. In the case that Si3N4 is coupled to a first metal contact, a second metal contact and a first metal layer, if Si3N4 is lifted due to a high stress, the first metal contact, the second metal contact or the first metal layer may be opened. That is, when the silicon nitride film is excessively exposed to the thermal stress, the silicon nitride film is lifted, and thus reliability of the device is seriously 15 reduced. Especially, the structural portion of the pad influenced by the thermal properties of the silicon nitride film in the NAND flash memory device is the adjacent portion between the trench stop silicon nitride film 112 and the second metal contact stop silicon nitride film 116. Accordingly, the stress for the silicon nitride film in that portion must be relieved in the back-end process of the NAND flash memory device, and countermeasures therefore must be provided.